EDN

Xilinx Spartan-6 FPGA User Guide Lite

What is the purpose of this paper? This paper gives potential users an easy-to-grasp idea of the device functions of Xilinx Spartan-6 FPGAs. It describes the functionality of these devices in far more ...
EDN

Design of a FPGA Configurable Logic Block for minimum energy and delay

Complete Layout, Design and Optimization of a FPGA Configurable Logic Block for minimum energy and delay: The CLB can function as one 8-bit adder, two 4-bit adders, a subtractor, multiplier, counter ...
Design-Reuse

Preservation of Circuit Structure and Timing during Fault Emulation in FPGA

This paper presents a technique that allows to preserve structure of a circuit according to a target technology during fault emulation in FPGA. The technique is not restricted to any target technology ...
Hackaday

Getting Good At FPGAs: Real World Pipelining

Parallelism is your friend when working with FPGAs. In fact, it’s often the biggest benefit of choosing an FPGA. The dragons hiding in programmable logic usually involve timing — chaining together ...
Embedded

FPGA Clock Schemes

One of the most important steps in the design process is to identify how many different clocks to use and how to route them. This article tells you how to use routing resources efficiently.
Design-Reuse

FPGA-Based DPLL Approach Delivers Wide-Lock Range

While analog phase-lock loops (PLLs) still have a home in communication equipment, there is a clear shift in the sector toward implementing digital PLLs (DPLLs) in comm ASIC designs. For example, in ...