SAN JOSE, CA--(Marketwire -09/04/12)- EVE, the leader in hardware/software co-verification, today announced that its ZeBu hardware-assisted verification platform and SystemVerilog methodology have ...

I’m happy to announce that we at Mentor have just released a fully-updated version of our popular UVM Cookbook, which is available online here. Cookbook Overview Diagram The Universal Verification ...

We have all been witnesses to the rapid improvements of the iPhone processor chip every year. With the iPhone 8 featuring the newest A11 Bionic at 10 nm FinFET with 4.3 billion transistors, I can’t ...

When I want to wear a certain clothing item, I take out it of the closet. When I go shopping, I add those clothes it to my closet and there are now new items for me to pick out in the future. A ...

My [LR’s] first exposure to hardware emulation happened circa 1995 upon visiting a major processor firm in Austin, Texas. Its lab was jam-packed from floor to ceiling with monstrous hardware emulators ...

The SystemVerilog universal verification methodology (UVM) is an efficient way to generate tests and check results for functional verification, best used for block level IC or FPGA or other “smaller” ...

Peer pressure is causing verification teams to adopt UVM but is it time for people to talk about alternatives to the UVM monolith. Blowing up UVM is something I ran on my own blog a few years ago.

This file type includes high resolution graphics and schematics when applicable. In the history of functional verification for complex chips, increasing automation has replaced tedious and expensive ...

I don’t know about you, but I am looking forward to the day where we won’t even have to go to the doctor’s office for an exam. Instead, we will all have scanners in our homes that will transmit full ...

It’s time for a frank discussion on the future of UVM. Given how UVM usage has grown and the number of teams that rely on it, I think this conversation has been a long time coming. Is continuing to ...