Henderson, NV – May 18, 2021 – Aldec, Inc., a pioneer in mixed HDL language simulation and hardware-assisted verification for FPGA and ASIC designs, provides industry’s most comprehensive ...
The latest release of Aldec’s Active-HDL supports IEEE 1076-2019 protected types, enabling engineers to simplify and abstract the construction of data structures for verification. Henderson, NV – ...
Aldec has said that it is now supplying the most comprehensive implementation of VHDL 2019 for both Windows and Linux platforms with the latest release of Riviera-PRO (release version 2021.04).
Aldec, a leader in mixed HDL language simulation and hardware-assisted verification for FPGA and ASIC designs, has updated Riviera-PRO to now include the 2020.08 revision of the open-source VHDL ...
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