EDN

Spectral content of NRZ test patterns

Many digital-communications systems use non-return-to-zero (NRZ) signaling, and system designers have created many NRZ test patterns to test and verify their products. These patterns usually either ...
Semiconductor Engineering

Reducing Chip Test Costs With AI-Based Pattern Optimization

The old adage “time is money” is highly applicable to the production testing of semiconductor devices. Every second that a wafer or chip is under test means that the next part cannot yet be tested.
EDN

Determining the best test patternsfor production test

Because I work for a provider of test tools that enable andproduce production test patterns, I am often asked what the best patterns areto use for production test. The answer depends on the device ...
Hackaday

Pocket-sized Test Pattern Generator Helps Check Those CRTs

[Nicholas Murray]’s Composite Test Pattern Generator is a beautifully-made, palm-sized tool that uses an ESP32-based development board to output different test patterns in PAL/NTSC. If one is checking ...
Electronic Design

Simulation Mismatches Can Foul Up Test-Pattern Verification

Design for testability (DFT) works to make a circuit more testable to ensure that it was manufactured correctly. Alfred Crouch explains the purpose of DFT in his book, Design-For-Test for Digital ICs ...
Electronic Design

Reduce Test/Diagnosis Cost with Optimized Scan-Pattern Ordering

Download this article in PDF format. Finding the right balance among test cost, test quality, and data collection for running diagnosis requires consideration of several competing factors. Luckily ...
Design-Reuse

Configurable VESA - VGA and DVI Test Pattern Generator

This paper is presented with the Video Graphics Array (VGA) and Digital Visual Interface - Digital (DVI-D) test pattern generator solution with display monitor timing specification as per the Video ...