EDN

VHDL Implementation of TCP/IP

The aim of the project was to traverse a packet through the TCP/IP suite using VHDL based ModelSim 6.3cSE. My role in the project was to design the flow of the packet through the TCP/IP layer and to ...
Ars Technica

Open Source VHDL (or similar) CPU Simulation Software

Hey all, my last semester of college we had to develop the microarchitecture for a RISC processor. My group was ultimately unsuccessful (our L2 cache had some serious issues), but I wouldn't mind ...
EDN

Tomasulo Out of Order Processor Design

(VHDL, ModelSim, Xilinx) Simulated and synthesized a processor with a clock frequency of 25 MHz. Used Tomasulo algorithm to dynamically schedule instructions and execute them in out of program order ...
Design-Reuse

Start-up OptNgn Offers a Floating Point VHDL Library as Open Source

Portland, Oregon -- April 16, 2008-- OptNgn today announced that it is offering a floating point VHDL library under the GPLv3 Open Source License. FPGA designers can now save months of coding and ...