IEEE

High-level statistical static timing analysis under process variation

Abstract: This paper proposes a promising statistical static timing analysis (SSTA) method for high-level design. The delay models obtained using gate-level SSTA are mapped to a timing graph of ...
IEEE

WCET Estimation for CNN Inference on FPGA SoC With Multi-DPU Engines

Abstract: The Deep Learning Processor Unit (DPU) released in the official Xilinx Vitis AI toolchain stands as a commercial off-the-shelf solution tailored for accelerating convolutional neural network ...