Jan 13, 2007 · what does npi mean NPI -> New Product Introduction Engineer NPI engineer's usually responsible for planning, directing, and coordinating customers' new product or …

Dec 23, 2025 · Hiring – Physical Design Engineer (RTL to GDSII, Cadence)” Hello ! I'm looking for a Physical Implementation Engineer for a semiconductor company in Paris. (Permanent …

Aug 8, 2016 · Hello all, I am currently working on layout in cadence virtuoso having calibre tool. In inverter while doing DRC,I am getting the following error which I am...

Nov 29, 2004 · HI, Recently i have installed hfss ver11 and ver12, both having the same problem when i try to open any hfss project file. hfss has encounter problem and need to close. Can …

May 15, 2025 · A RTL design engineer role where you get a chance to focus exclusively on IP development or some protocol implementation. As you write more and more RTL, your level of …

Feb 21, 2018 · Hi All, i sometimes open multiple verdi waveforms to comapre against different simulations. is there a way to view the full path of the fsdb being currently loaded in a …

Dec 8, 2012 · Hi, I simulate multiple test cases having same signal lists. So, I got multiple **.fsdb files such as TC_01.fsdb, TC_02.fsdb and so on. I wanna get signals simultaneously from …

Aug 25, 2007 · West Coast Activity points 66,416 jed2eqn If the security fuse has been blown, you will not be able to read the PLD in question .. Reverse-engineering is possible, but it will …

Dec 19, 2008 · asic verification interview questions Hi every one, Yesterday i got an interview with NVIDIA. They asked one intresting interview question. What if design engineer and verification …

Jun 30, 2011 · Can anyone help me about some drc error such as : pp.en => enclosure of p0 > 20um lup.3p => nwell pick up od to pmos space > 30um and error of empty area of chip? im ...